Magnetoresistive Random Access Memory (MRAM), based on the integration of silicon CMOS with MTJ technology, is a major emerging technology that is highly competitive with existing semiconductor memories such as SRAM, DRAM, Flash, etc. Related information on this subject is provided by S. Parkin et. al in “Exchange based magnetic tunnel junctions and application to non-volatile MRAM” J. Appl. Phys., Vol. 82, p. 5823-5833 (1999), and by S. Tehrani et. al in “Progress and Outlook for MRAM Technology”, IEEE Trans. on Magn., Vol. 35, p. 2814-2819 (1999).
A MRAM device is generally comprised of an array of parallel first conductive lines on a horizontal plane, an array of parallel second conductive lines on a second horizontal plane spaced above and formed in a direction orthogonal to the first conductive lines, and an MTJ element (bit) interposed between a first conductive line and a second conductive line at each crossover location in a cross-point architecture. A first conductive line may be a word line while a second conductive line is a bit line or vice versa. Alternatively, a first conductive line may be a bottom electrode that is a sectioned line while a second conductive line is a bit line (or word line). There are typically other devices including transistors and diodes below the-array of first conductive lines as well as peripheral circuits used to select certain MRAM cells within the MRAM array for read or write operations.
An MTJ element may be based on a tunneling magneto-resistance (TMR) effect wherein a stack of layers has a configuration in which two ferromagnetic layers are separated by a thin non-magnetic dielectric layer. In an MRAM device, the MTJ element is formed between a bottom electrode such as a first conductive line and a top electrode which is a second conductive line. An MTJ stack of layers that are subsequently patterned to yield an MTJ element may be formed in a so-called bottom spin valve configuration by sequentially depositing a seed layer, an anti-ferromagnetic (AFM) pinning layer, a ferromagnetic “pinned” layer, a thin tunnel barrier layer, a ferromagnetic “free” layer, and a capping layer. The AFM layer holds the magnetic moment of the pinned layer in a fixed direction. In a MRAM MTJ, the free layer is preferably made of NiFe because of its reproducible and reliable switching characteristics as demonstrated by a low switching field (Hc) and switching field uniformity (σHc). Alternatively, an MTJ stack may have a top spin valve configuration in which a free layer is formed on a seed layer followed by sequentially forming a tunnel barrier layer, a pinned layer, AFM layer, and a capping layer.
The pinned layer has a magnetic moment that is fixed in the “y” direction, for example, by exchange coupling with the adjacent AFM layer that is also magnetized in the “y” direction. The free layer has a magnetic moment that is either parallel or anti-parallel to the magnetic moment in the pinned layer. The tunnel barrier layer is thin enough that a current through it can be established by quantum mechanical tunneling of conduction electrons. The magnetic moment of the free layer may change in response to external magnetic fields and it is the relative orientation of the magnetic moments between the free and pinned layers that determines the tunneling current and therefore the resistance of the tunneling junction. When a sense current is passed from the top electrode to the bottom electrode in a direction perpendicular to the MTJ layers, a lower resistance is detected when the magnetization directions of the free and pinned layers are in a parallel state (“0” memory state) and a higher resistance is noted when they are in an anti-parallel state or “1” memory state.
In a read operation, the information stored in an MRAM cell is read by sensing the magnetic state (resistance level) of the MTJ element through a sense current flowing top to bottom through the cell in a current perpendicular to plane (CPP) configuration. During a write operation, information is written to the MRAM cell by changing the magnetic state in the free layer to an appropriate one by generating external magnetic fields as a result of applying bit line and word line currents in two crossing conductive lines, either above or below the MTJ element. In certain MRAM architectures, the top electrode or the bottom electrode participates in both read and write operations. The MTJ memory cells are inserted into the back end of a CMOS process. A high speed version of MRAM architecture consists of a cell with an access transistor and a plurality of MTJ (1T1MTJ) cells in the MRAM array.
A high performance MTJ element is characterized by a high magnetoresistive (MR) ratio or tunneling magnetoresistive ratio (TMR) which is dR/R where R is the minimum resistance of the MTJ element and dR is the change in resistance observed by changing the magnetic state of the free layer. A low magnetostriction (λs) value of about 1×10−6 or less is also desirable for MRAM applications. The keys to a high performance MTJ element for MRAM are (a) well controlled magnetization of a pinned layer that has a large exchange field and high thermal stability, (b) integrity of the tunnel barrier layer and, (c) well controlled magnetization and switching of the free layer. In order to achieve good barrier properties such as a specific junction resistance×area (RA) value and a high breakdown voltage (Vb), it is necessary to have a uniform tunnel barrier layer which is free of pinholes that is promoted by a smooth and densely packed growth in the AFM and pinned layers. Although a high RA value of about 10000 ohm-μm2 is acceptable for a large area (A), RA should be relatively small (about 1000 ohm-μm2) for smaller areas. Otherwise, R would be too high to match the resistance of the transistor which is connected to the MTJ.
For (a) above, the pinned layer of a MTJ element is typically made of a synthetic antiferromagnetic (SyAF) configuration such as CoFe/Ru/CoFe where Ru is a coupling layer sandwiched between a AP2 layer adjacent to an AFM layer and a AP1 layer next to the tunnel barrier. Use of a SyAF pinned layer not only improves thermal stability but also minimizes the coupling field between the pinned layer and free layer, thereby reducing the offset field. For (b), the tunnel barrier commonly used is either a thin layer of amorphous AlOx or crystalline MgO. To optimize (c) above, the free layer is best made of a thin (<50 Angstrom thick) permalloy (NiFe) film because of its reproducible and reliable switching characteristics.
Generally, the purpose of the capping layer is to protect underlying layers in the MTJ during etching and other process steps and to function as an electrical contact to an overlying conductive line. The typical capping layer for an MTJ stack is a non-magnetic conductive metal such as Ta or TaN. During thermal annealing, Ta is capable of gettering oxygen atoms originating in the adjacent NiFe free layer. Consequently, the NiFe free layer is less oxygen contaminated and a more distinct boundary between the tunnel barrier layer and NiFe free layer is thereby obtained to improve dR/R. The disadvantage of using a Ta capping layer is that Ta diffuses into NiFe during thermal annealing, especially at high annealing temperatures (i.e. >250° C.) to produce an alloy that not only reduces free layer moment (Bs) but makes NiFe very magnetostrictive with a λs of ≧5×10−6. Thus, alternative capping layer materials are desirable that minimize inter-diffusion between a free layer and capping layer, serve as a good oxygen getter material, and enable both a high MR ratio and low λs value to be achieved in MTJs for advanced MRAM and TMR read head technologies.
A MRAM circuit chip typically consists of millions of MTJ bits formed on a substrate that has CMOS devices. After completing the MRAM circuits, MRAM MTJs are subjected to electrical/magnetic probing by using a quasistatic tester. One of the critical measurements obtained by the quasistatic test is error count (EC) that represents the number of defective MTJ bits. The procedure for EC measurement involves a first step of applying a 150 Oe magnetic field in the easy axis direction to re-intialize all the MTJ bits on the MRAM chip to a “0” state (i.e. free layer magnetization is parallel to pinned layer magnetization). Then, in a second step, currents are applied to the word line (WL) and bit line (BL) to switch the free layer into a “1” state (i.e. where the free layer and pinned layer magnetizations are anti-parallel). In a third step, a read operation is performed to determine how many MTJ bits in each MRAM chip failed the intended switching from “0” to “1” thereby providing an EC0 value. Similarly, an EC1 value is determined by measuring the number of MTJ bits whose free layer magnetization was first re-initialized to a “1” state, then switched to a “0” state by writing from WL and BL, and finally read to count the number of MTJ bits which failed to switch. The total EC is EC0+EC1. For a MTJ MRAM to be viable in manufacturing, a good product yield for the 1 -Mbit MRAM chip is necessary which means an EC of less than 10 parts per million (ppm), and preferably less than 5 ppm. Current MTJ MRAMs have an EC on the order of 20 to 1000 ppm. Therefore, an improved MTJ configuration is needed to reduce EC to an acceptable level.
A routine search of the prior art was conducted and the following references were found. In U.S. Patent Application 2007/0015293, an oxygen surfactant layer (OSL) is formed between a composite CoFeB/CoFe AP1 pinned layer and an AlOx tunnel barrier to improve smoothness in the AlOx layer. U.S. Pat. No. 7,045,841 describes an OSL formed between an upper ferromagnetic layer made of CoFe (or CoFe/NiFe) and an AlOx tunnel barrier.
U.S. Patent Application 2007/0015294 teaches an AP1 layer made of Co75Fe25 below an AlOx tunnel barrier. According to U.S. Patent Application 2006/0017081, an interface layer made of CoFe may be formed between an amorphous fixed layer (CoFeB) and a tunnel barrier in a MTJ element.
U.S. Pat. No. 7,067,331 discloses an amorphous CoFeB fixed layer that contacts an aluminum oxide tunnel barrier. U.S. Pat. No. 6,818,458 describes a self pinned multi-layer having a CoFe alloy such as CoFeHf or CoFeZr that contacts an AlOx tunnel barrier. U.S. Patent Application 2006/0211198 discloses a Ta/Ru capping layer for the bottom conductive electrode where the Ru is etched away to form an amorphous Ta capping layer. U.S. Patent Application 2005/0276099 shows a Ru/Ta/Ru capping layer configuration for improving dR/R in a MTJ element.